This invention relates to digital to analog (D/A) converters and more particularly to ladderless D/A converters suitable to be fabricated in monolithic form on a single chip utilizing CMOS technology.
The electronic field is replete with applications for D/A converter systems. For example, D/A converters may be used as peripheral units interfacing between microprocessors (MPU's), computers and other systems requiring real time analog voltage inputs. D/A converters are also required in applications where any type of digital number (BCD, binary, etc.) must be converted to a corresponding analog output.
Most contemporary D/A converter systems available today are of the discrete type and comprise resistive ladder termination networks and operational amplifiers. These components result in a D/A converter of relatively large size and high cost. The resistive ladder network typically is fabricated in a matrix using diffused resistors or thin film resistors. Because the accuracy of these converters is directly proportional to the precision of the relative values of the resistors, much care is required in the fabrication thereof. Typically, however, the resistors must be trimmed in value, for instance, by laser trimming or other methods to meet the tolerance established for the system. This process is expensive and undesirous. Moreover, the ladder network makes it virtually impossible to fabricate such converters on a single monolithic chip. Therefore, a need exists for a D/A converter system which requires no such precision components as a resistive ladder termination network. Such a system could be fabricated on a single chip and require no trimming. Hence, size and cost could be reduced while maintaining system accuracy.
Another critical problem of the prior art is related to the inherent inaccuracies of operational amplifiers. The offset voltages associated with the operational amplifiers produce errors in these systems which must be compensated thereof. Typically, the prior art includes precision adjusting components to provide zeroing of the system and to eliminate the variations caused by the offsets of the amplifiers. These components further increase not only the size but the cost of the prior art systems. Moreover, these converters require constant adjustment to maintain system accuracy. Thus, it is desirous to eliminate the need for such precision components by providing a D/A converter having self zeroing and offset compensation. Where such self-correction is accomplished for each conversion cycle, sensitivity to temperature changes is minimized. Such a system would reduce cost, inaccuracies, eliminate any need for operator attention, and lend itself to being fabricated on a single chip to further reduce the size thereof, all of which are very desirous goals. Moreover, such a D/A converter could be fabricated using CMOS technology which would also reduce power drain to reduce power requirements.
In an attempt to overcome the deficiencies of the prior art discrete converters, one contemporary converter system eliminates the need for the ladder network, and is capable of being fabricated using MOS technology. However, this system suffers from several deficiencies. Most significantly, this system does not compensate for the offset voltages of the included operational amplifiers. These errors arise between the input digital signal and the generation of the output analog signal. In an attempt to overcome these errors, several successive conversion cycles are required by the system which, therefore, time limits the system. Additionally, both positive and negative reference voltages are required to provide conversion of binary numbers of both polarities. To insure accuracy, the system requires that these voltages be equal in absolute magnitude. This requires complex and precision power supplies which increase the cost of the system. Moreover, this system, to provide outputs of both polarities, requires the use of an internal up-down counter which further increases the system complexity and hence cost. Therefore, a need exists for a single chip, CMOS D/A converter which requires only a single reference voltage and which can provide analog outputs of both polarities therefrom, and which is self-correcting for each conversion cycle.
Furthermore, the above prior art converter is capable of only receiving digital input numbers in binary form and is limited to a six-bit input. Thus, there is a requirement for an improved converter which is adaptable to receive any type of binary coded number, i.e., BCD, binary or any other desired code. In conjunction therewith, the input of such a converter should not be limited to the number of input bits -- except for practical realities.